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Data Sheet
Figure 108 shows the HSDC transfer protocol for HGAP = 0,
HXFER[1:0] = 00 and HSAPOL = 0. Note that the HSDC
interface sets a data bit on the HSD line every HSCLK high-to-
low transition and the value of Bit HSIZE is irrelevant.
Figure 109 shows the HSDC transfer protocol for HSIZE = 0,
HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0. Note that the
HSDC interface introduces a seven-HSCLK cycles gap between
every 32-bit word.
Figure 110 shows the HSDC transfer protocol for HSIZE = 1,
HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0. Note that the
HSDC interface introduces a seven-HSCLK cycles gap between
every 8-bit word.
Table 25. Communication Times for Various HSDC Settings
ADE7880
See Table 52 for the HSDC_CFG register and descriptions for
the HCLK, HSIZE, HGAP, HXFER[1:0], and HSAPOL bits.
Table 25 lists the time it takes to execute an HSDC data transfer
for all HSDC_CFG register settings. For some settings, the
transfer time is less than 125 μs (8 kHz), the waveform sample
registers update rate. This means the HSDC port transmits data
every sampling cycle. For settings in which the transfer time is
greater than 125 μs, the HSDC port transmits data only in the
first of two consecutive 8 kHz sampling cycles. This means it
transmits registers at an effective rate of 4 kHz.
HXFER[1:0]
00
00
00
00
00
00
01
01
01
01
01
01
10
10
10
10
10
10
HGAP
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
HSIZE 1
N/A
N/A
0
0
1
1
N/A
N/A
0
0
1
1
N/A
N/A
0
0
1
1
HCLK
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Communication Time (μs)
64
128
77.125
154.25
119.25
238.25
28
56
33.25
66.5
51.625
103.25
36
72
43
86
66.625
133.25
1
N/A means not applicable.
HSCLK
HSD
31
IAVW (32-BIT)
0 31
VAWV (32-BIT)
0 31
IBWV (32-BIT)
0
31
CFVAR (32-BIT)
0
HSA
Figure 108. HSDC Communication for HGAP = 0, HXFER[1:0] = 00, and HSAPOL = 0; HSIZE Is Irrelevant
Rev. A | Page 79 of 104
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